FPGA is an integrated circuit whose functionalities are designated by users of the FPGA. A FPGA consists generally of a great number of logic cells.
A basic FPGA logic cell (referred below as LC) is shown as in FIG. 1, which comprises a look-up table (LUT) 102 and a D flip-flop (DFF) 108. The 4-input LUT 102 is shown to have a set of 16 configuration memory cells, which can be configured or programmed to compute any 4-input combinational logic function. Note that as the details of such programming circuitry is not relevant to this type of invention, it is not shown in FIG. 1. The output of the LUT 102 is not only directly connected to an output of the LC, but also fed into the D input terminal of DFF 108, the Q output of which is available as another LC output. Also not shown, the flip-flop 108 may also be provided with clock enable terminal, set terminal and/or reset terminal. Within the logic cell, multiplexers (MUX) and other logics may be provided to allow the Q output terminal of the flip-flop be connected to some input terminal of the LUT. In addition, output signals of logic cells may be routed to input terminals of logic cells via some general-purpose interconnection network, in order to build any given digital logic circuit.
The basic logic cell is logically complete. However, there exist demands for more area and timing efficient and/or placement-friendly logic cells and integrated circuits therefrom.